The present invention relates generally to delay locked loop (DLL) circuits, and more particularly to circuitry for providing “false-lock-free” phase comparison in a delay locked loop circuit.
Delay locked loops (DLLs) are widely used in analog circuit design. The capability of a DLL to provide timing of clock signals that are precisely delayed relative to a reference clock signal is very valuable in many applications, such as circuits for eliminating clock skew, multi-phase clock generators, and clock/data recovery circuitry.
FIG. 1 shows a conventional delay locked loop circuit 20 including a delay line 21. Delay line 21 includes N delay cells 40-1, 40-2 . . . 40-N as shown, wherein each delay cell includes a delay control input connected to delay control conductor 29. A reference clock CKref is applied as an input to the first delay cell 40-1 and a first input of a phase detector 24. The output d1 of the first delay cell 40-1 is connected to the input of the second delay cell 40-2. Similarly, the output d2 of the second delay cell 40-2 is connected to the input of the third delay cell 40-3, and so forth. The input of first delay cell 40-1 is connected by conductor 16 to receive a reference clock signal CKref. The output dN of the last delay cell 40-N is connected to a second input of phase detector 24. A control voltage on a delay control conductor 29 can be varied to adjust the delay through delay line 21. Thus, delay line 21 is made up by cascading multiple identical delay cells 40 the delay of which is set by the delay control signal on conductor 29.
Phase detector 24 produces a signal UP on conductor 25 and a signal DOWN on conductor 26, both of which are applied as inputs to a loop filter circuit 28. Loop filter circuit 28 is schematically illustrated as including a first current source 72 coupled between a power supply voltage VDD and one terminal of a switch 73, the other terminal of which is connected to delay control conductor 29. Switch 73 is controlled by the UP signal on conductor 25. A capacitor 76 is coupled between delay control conductor 29 and ground. A second switch 74 is connected between delay control conductor 29 and one terminal of a second current source 75, the other terminal of which is connected to ground. Switch 74 is controlled by the DOWN signal on conductor 26. The output of loop filter circuit 28 provides the delay control voltage on delay control conductor 29. Capacitor 76 acts as a loop filter, and the structure including switchable current sources 72 and 75 and capacitor 76 is commonly referred to as a charge pump.
In operation, a pulse of CKref ripples through delay line 21, creating a different phase of delayed clock signal at the respective outputs of each of the delay cells 40-1 through 40-N. Phase detector 24 compares the output pulse produced at the end of delay line 21 with the CKref pulse delayed by one reference clock cycle T. The CKref pulse delayed by one cycle time T is hereinafter referred to as the “next incoming pulse of CKref”. The output of phase detector 24 controls loop filter circuit 28, which typically is a charge pump circuit. If the delay between the rising edge of the initial pulse of CKref and the rising edge of the resulting first pulse produced at the output dN of last delay cell 40-N is too long, phase detector 24 senses that condition and turns on switch 73 to dump more charge from current source 72 into capacitor 76 and thereby raise the voltage on delay control conductor 29, since a higher control voltage applied to the delay cells reduces the signal delay through them.
The feedback loop therefore operates to lock the rising edge of the output of the last delay cell 40-N with the rising edge of the next pulse of CKref, thereby ensuring that the total delay through delay line 21 is precisely equal to the period T of CKref. Similarly, if the delay through delay line 21 is too short, the feedback loop reduces the voltage across capacitor 76 so as to increase the delay time to the value of the reference clock period T in order to cause DLL 20 to acquire or maintain a correct lock condition.
Each of the N delay cells 40 produces a delay exactly equal to T/N, as indicated by reference numerals 78 in FIG. 2. Due to the ability of the feedback loop to adjust the delay control voltage on conductor 29, the delay through delay line 21 is insensitive to variations in parameters such as chip temperature, integrated circuit manufacturing process parameters, power supply voltage, and the like that would otherwise affect the delay through each cell.
In a conventional DLL, only the last delay cell output of the delay line is compared to the the next incoming pulse of CKref by the phase detector, which immediately produces an indication of the phase difference between the input dN and an incoming pulse of CKref. A problem of the conventional DLL of FIG. 1 is that it may try to “lock onto” an incorrect pulse that is delayed by an integer number nT of periods of the input clock, where n is greater than 1. This is condition known as a “false-lock” condition.
The timing diagrams of FIGS. 3A and 3B illustrate a “correct lock” condition and a “false-lock” condition, respectively, in the DLL of FIG. 1. Note that a typical prior art phase detector can “lock in” either the correct lock condition shown in FIG. 3A or the false-lock condition of FIG. 3B.
FIG. 3A illustrates a “correct lock” condition in a DLL having (as an example) only three delay cells in its delay line. The DLL receives a reference clock CKref and produces delay cell outputs d1, d2 and d3 which are shown in FIG. 3A. Since the feedback loop forces the total delay through the delay line 21 to be equal to T, the delay through each delay cell is equal to T/3. Arrow 10 indicates when the delay through the first delay cell occurs, arrow 111 indicates when the delay through the second delay cell occurs, and arrow 12 indicates when the delay through the third delay cell occurs. The rising edge C of the second pulse of the output d3 is shown as being correctly locked into alignment with the rising edge A of the second pulse of CKref. Arrow B indicates the correct locking time for the DLL.
Similarly, FIG. 3B also illustrates the reference clock CKref and the outputs d1, d2 and d3 of a DLL including a delay line having only three delay cell. However, in this case the DLL is in a “false-lock” condition wherein the feedback loop forces the total delay through the delay line to be equal to 2T rather than the correct delay T. The delay through each delay cell therefore is 2T/3 instead of T/3, and arrows 10A, 11A and 12A indicate the times during which the delay through the each of the three delay cells occurs. When a DLL is in a false-lock condition, it generates a delay time nT that is equal to an integral multiple n of T, where n is greater than 1. Such a false-lock condition usually is an undesirable condition, especially if it persists, because it would produce unintended signal delays, which would be likely to cause circuit malfunctions and sometimes may have disastrous results.
U.S. Pat. No. 6,239,634 entitled “Apparatus and Method for Ensuring the Correct Start-up and Locking of a Delay Locked Loop”, issued May 29, 2001, discloses one approach to preventing a false-lock condition in a DLL by clamping the delay line control voltage to a proper level during start-up operation or a reset operation in order to ensure locking in of a “correct lock” condition rather than a “false lock” condition. In order to accomplish that, the precise delay characteristics of the voltage controlled delay line must be accurately known so that the loop capacitor of the loop filter can be charged or discharged to the correct control voltage. This approach clamps or presets the loop filter output voltage to a certain level in order to force the total signal delay through the delay line to be close to its normal value T. Then the phase detector can readily bring the delay locked loop to the correct lock condition and avoid a false-lock condition.
A problem with this approach is that the value at which to pre-set the loop filter output voltage must be known. However, this value is highly dependent on manufacturing process parameter variations, temperature variations, power supply voltage variations, and period/frequency of CKref. This makes it difficult to provide the preset or clamp value of the loop filter output voltage to with a preset or clamp value that can cause the loop to reliably lock on the correct rising edge of the output voltage dN of the last delay cell. The foregoing technique is capable of guaranteeing only a proper start-up operation. If the prior art DLL 20 is ever caused to be in a false-lock condition, there is no mechanism to allow the feedback loop to recover to a correct lock condition.
Unfortunately, the “robustness” of the loop operation described in U.S. Pat. No. 6,239,634 is compromised because a correct lock condition can only be guaranteed by performing a reset operation.
Another known approach to dealing with a false-lock condition in a DLL is to “measure” the delay time/frequency range by monitoring the output of all of the delay cells in the delay line. If the delay time/frequency is outside of a proper range, the phase detector control of charging and discharging the loop filter capacitor is disabled, and a monitoring circuit takes over to charge or discharge the loop filter capacitor until the delay through the delay line falls within the proper range. Specifically, if that delay falls outside of a normal “correct lock” range, the monitoring circuit takes over and drives the loop filter capacitor to an approximate voltage in a correct predetermined range. This allows the feedback loop and the phase detector to take over operation and re-establish a correct lock condition. The foregoing technique is illustrated in U.S. Pat. No. 6,326,826 entitled “Wide Frequency-Range Delay-Locked Loop Circuit” issued Dec. 4, 2001 and the article “CMOS DLL-based 2-V 3.2-ps Jitter 1-Ghz Clock Synthesizer and Temperature-Compensated Tunable Oscillator”, IEEE JSSC, Vol. 36, No. 3, March 2001.
Shortcomings of the foregoing approaches include the need for the additional monitoring circuit referred to and also additional analog components shown in the two foregoing prior art references. Also, the monitoring circuitry and associated correction circuitry designed for use in conjunction with a particular delay line usually would not be usable for a different delay line having a different number of delay cells without extensive modification.
Thus, there is an unmet need for a DLL circuit that avoids false-lock conditions.
There also is an unmet need for a DLL circuit that readily automatically recovers from false-lock conditions.
There also is an unmet need for a DLL circuit that avoids the need to provide additional circuitry to preset or clamp the output voltage of a loop filter circuit in order to enable the DLL circuit to reliably establish and/or maintain a correct lock condition.
There also is an unmet need for a DLL circuit that avoids the need for a reset operation in order to ensure a correct lock condition.
There also is an unmet need for a DLL circuit that avoids the need to provide a monitoring circuit to take over charging or discharging of the loop filter capacitor until the DLL feedback loop is able to take over and reliably establish a correct lock condition.
There also is an unmet need for a DLL circuit design the basic structure of which is essentially independent of the number of delay cells in a delay line of the DLL circuit.
There also is an unmet need for a DLL circuit including a phase detector having substantially increased information monitoring capability that enables the DLL circuit to avoid false-lock conditions.